This invention relates in general to multiprocessor computing systems and, more particularly, to a multiprocessor computing system capable of selectively implementing a register pipe between a pair of processing engines of the multiprocessor computing system to facilitate transfer of data therebetween.
Generally speaking, computer programs may be executed by computing systems in various modes. For instance, any of a single instruction stream single data stream (SISD) mode; a single instruction stream multiple data stream (SIMD) mode; a single program multiple data stream (SPMD) mode; or a multiple instruction stream multiple data stream (MIMD) mode may be used to execute a typical computer program.
In SISD mode, a computer program generates and executes a single instruction stream to produce a single data stream or result. This is commonly referred to as a. classical uniprocessor mode of operation. In addition, operation in a SISD mode often occurs even in multiprocessor or parallel systems. This may occur due to programming techniques, algorithmic serialization, or legacy from past implementations.
In many multiple processor or multiprocessor systems, computer programs may be executed in SIMD mode. In this mode, several pieces of data are simultaneously processed by a single instruction. Thus, several processors or processing elements may operate on a same instruction but with separate data streams. In the SPMD variant of this mode, each processor executes a same program, which is fetched independently, and operates on its own data stream. Operation in SPMD mode allows the various processors to be attached only to local memory and communicate results over a message passing fabric or network.
In other multiprocessor systems, programs may be executed in a MIMD mode where each processor operates independently not only on its own data streams, but also on its own instruction streams. Processing in this mode is facilitated by either shared storage or by passing messages between the processors.
Classical multiprocessors, or shared memory processors (SMPs), allow programs to be executed in either SISD or MIMD modes, and sometimes in SPMD mode. However, these machines suffer from memory contention constraints. Because of this, the granularity of parallelism is usually limited to a level at which it is beneficial to execute several program-managed threads or processes which communicate by sharing memory.
When input values for an operation to be executed by one processor are results (i.e., output values) of another instruction executed by another processor within a shared memory multiprocessor environment, the processing of the operation becomes more complex. First, in order for the first processor to obtain the results to be utilized as input values, the second processor must first store the output values to memory so that the first processor may then retrieve the results from memory. As will be appreciated, these prerequisite steps consume additional instructions and clock cycles to store and load values from one processor to the other, thereby creating substantial inefficiencies and undesirable consumption of processor power. Also, the execution of instructions requiring the results of other executed instructions as inputs requires that the processors be synchronized to ensure that the first processor is accessing the appropriate results in memory and not some prior, outdated values. Conventionally, complicated procedures of data management are employed to ensure that memory coherency is maintained in the system.
In view of these processing complexities, it is desirable to facilitate a more efficient transfer of information between processing engines in a multiprocessor computer system.
Provided herein, therefore, is a register pipe facility disposed between a pair of processing engines in a multiprocessor computer system. This register pipe allows data to be transferred from a first processing engine to a second processing engine without passing through memory of the computer system. Further, the register pipe provided herein can be implemented dynamically using general purpose registers of the processing engines themselves to be connected by the pipe within the multiprocessor computer system.
To summarize, in one aspect, provided herein is a method of transferring data between a first processing engine and a second processing engine. The method includes: establishing a register pipe-between the first processing engine and the second processing engine, the register pipe may include at least one first register in the first processing engine and at least one second register in the second processing engine; and transferring data between the first processing engine and the second processing engine using the register pipe, wherein data is transferred between the first and second processing engines without passing through main memory of the multiprocessor computer system to which the first processing engine and second processing engine belong.
In another aspect, a system of transferring data between a first processing engine and a second processing engine is provided. The system includes means for establishing a register pipe between the first processing engine and the second processing engine, wherein the register pipe may include at least one first register of the first processing engine and at least one second register of the second processing engine. The system further includes means for transferring data between the first processing engine and the second processing engine using the register pipe, wherein data is transferred between the first and second processing engines without passing through memory of the multiprocessor computer system to which the first and second processing systems belong.
In still another aspect, a multiprocessor computer system is provided which includes a first processing engine and a second processing engine. The multiprocessor computer system comprises a register pipe between the first processing engine and the second processing engine, wherein the register pipe includes at least one first register in the first processing engine and at least one second register in the second processing engine. The first processing engine and the second processing engine are adapted to transfer data therebetween using the register pipe and without passing the data through memory of the multiprocessor computer system.
In a further aspect, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine is provided to perform a method of transferring data between a first processing engine and a second processing engine. The method includes: establishing a register pipe between the first processing engine and the second processing engine, the register pipe may include at least one first register in the first processing engine and at least one second register in the second processing engine; and transferring data between the first processing engine and the second processing engine using the register pipe, wherein data is transferred between the first and second processing engines without passing through main memory of the multiprocessor computer system to which the first processing engine and the second processing engine belong.
To restate, provided herein is a register pipe facility and technique for establishing a register pipe between a pair of processing engines of a multiprocessor computer system to facilitate transfer of data therebetween without using, for example, main memory of the computer system. In a parallel processing system which is loosely coupled, the register pipes presented herein provide a faster more efficient means to communicate data between processors using a finer grain (i.e., smaller pieces of data). Specifically, loosely coupled machines typically use input/output (I/O) to move data from machine to machine. This usually means the movement of data results into memory, where the results are buffered, and then the execution of a program which moves the data either synchronously or asynchronously from memory to the other machine. This approach is contrasted with the register pipes facility presented herein which simply targets a pipe register with a data result.
In a tightly coupled parallel processing system (SMP or memory sharing system) register pipes as presented herein are still more efficient. In such a system, data results must conventionally be stored to memory, the processors then synchronized, and the data fetched to the target machine. This is contrasted with simply targeting a register pipe with a data result to be transferred from one machine to another in accordance with the principles of the present invention.
In a massive cache machine such as described in the cross-referenced and incorporated application entitled xe2x80x9cComposite Uniprocessor,xe2x80x9d or other SIMD capable machine, data results must still be stored and then fetched using joined registers. In accordance with the present invention, data results are transferred simply by targeting a register pipe with the result. Register pipes as presented herein are a way for multiprocessor machines to avoid storing data results, then loading the results from one engine when needed by another engine. While storing data before loading is only an additional instruction, this additional instruction can add up if it is an inner loop of a program.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered part of the claimed invention.